meeting date: 17 may 2005
attending:	Todd Westerhoff, Arpad Muranyi, Donald Telian,
Mike LaBonte, Barry Katz, Scott McMorrow, Ken Willis

Summary of last meeting, get Ken Willis up to speed.

Review of building blocks (Mike's AR)
- What happened to controlled sources?
  - E, F, G, H style controlled sources with explicit control
    terminals were eliminated because they can be replaced
    by "fixed" sources with voltage/current expressions that
    reference other terminals as control inputs.
    - This allows for any number of control inputs.
    - Issue: control inputs as parameters create implicit connectivity.
      - Nodes available for use as control inputs can be restricted
        to nodes in the calling circuit. No hierarchy jumping.
- Should ideal_tline have loss tangent? No.
- Agreed changes:
  - Eliminate lossy tlines.
  - Add s-param models.
    - sparam2 and sparam4
  - Capacitor code needs charge conservation tweaks.
  - Add initial condition setting to capacitor & inductor.
AR: Mike will send out updated building blocks file

Discussion of parameter expressions
- Top level circuit has connectivity AND parameters.
- Can parameters have equations?
  - Equations are allowed in building blocks and template modules.
  - IBIS [External Circuit] instance calls may invoke parameters
    with numeric and simple text values only.
    - Table inputs allowed as comma-separated text.
- Discussion turned to utilization of what? - something missing here
AR: Arpad will investigate expression languages to see if an existing definition will do

Revisit the idea of IBIS adopting an existing SPICE language
- It's unfortunate IBIS rallied around least-common-denominator Berkeley SPICE.
- Todd contacted a friend at Synopsys who will try to arrange a meeting (Todd's AR)
- Do we want a vendor to contribute their language?
  - Some discussion of whether the language should be used as-is and
    only referenced, or if the text is copied into another document.
  - Would require a future BIRD.
  - The Verilog-A macromodel approach requires no BIRD vote.
- Who's SPICE would it be?
  - It is not even clear yet that Cadence is willing to contribute KSPICE.
    - KSPICE will not make it through the IBIS committee.
    - Will Mentor agree to KSPICE? Their group seems to be VHDL-AMS centric.
  - Only HSPICE creates a level playing field, but it will fail politically.
    - One idea is to reference the HSPICE manual, without transistors.
  - The language will become a defacto standard, 1-vendor solution.
- Do we want to create a language from scratch?  Then why not use an existing
  language, such as Verilog-A(MS) which is very similar to SPICE?

Do we present the competing ideas at DAC?
- Discuss next meeting